4th RISC-V Workshop

Cambridge, Massachusetts
Tuesday, July 12, 2016

4th RISC-V Workshop

Tuesday, July 12, 2016 8:00 AM - Wednesday, July 13, 2016 5:00 PM (Eastern Time)

32 Vasser Street
Cambridge, Massachusetts 02139
United States

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Please ​join ​us ​for ​the ​4th ​RISC-V ​Workshop, ​which ​will ​be ​hosted ​at ​MIT’s ​Computer ​Science ​and ​Artificial ​Intelligence ​Lab ​(CSAIL) ​building ​this ​coming ​July ​12-13, ​2016. ​The ​goals ​of ​the ​workshop ​are ​for ​the ​community ​to ​share ​information ​about ​recent ​activity ​in ​various ​RISC-V ​projects ​underway ​around ​the ​globe, ​and ​to ​build ​consensus ​on ​future ​steps ​with ​the ​RISC-V ​ISA.

We ​are ​seeking ​proposals ​for ​talks ​and ​posters, ​with ​abstract ​submissions ​due ​by ​11:59:59PM ​Pacific ​Daylight ​Savings ​Time, ​Saturday, ​May ​7 ​ ​and ​notification ​by ​Sunday, ​May ​22. ​Please ​check ​your ​registration ​ ​confirmation ​page ​with ​more ​details. ​

RISC-V ​(pronounced ​“risk-five”) ​is ​a ​new ​instruction ​set ​architecture ​(ISA) ​that ​was ​originally ​designed ​to ​support ​computer ​architecture ​research ​and ​education ​and ​is ​now ​set ​to ​become ​a ​standard ​open ​architecture ​for ​industry ​implementations ​under ​the ​governance ​of ​the ​RISC-V ​Foundation. ​RISC-V ​was ​originally ​developed ​in ​the ​Computer ​Science ​Division ​of ​the ​EECS ​Department ​at ​the ​University ​of ​California, ​Berkeley.

The ​RISC-V ​Foundation, ​a ​non-profit ​corporation ​controlled ​by ​its ​members, ​directs ​the ​future ​development ​and ​drives ​the ​adoption ​of ​the ​RISC-V ​ISA. ​Members ​of ​the ​RISC-V ​Foundation ​have ​access ​to ​and ​participate ​in ​the ​development ​of ​the ​RISC-V ​ISA ​specifications ​and ​related ​HW ​/ ​SW ​ecosystem.

Learn ​More: ​http://www.riscv.org

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